The present invention relates to a method of manufacturing a semiconductor device. The present invention has particular applicability to manufacturing high density semiconductor devices with submicron design features.
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. This trend has resulted in continued shrinking of device and circuit dimensions and features. In integrated circuits having transistors, for example, one very important process step is the formation of the gate, source, and drain regions for each of the transistors and, in particular, the dimensions of the gate, source, and drain regions. Often, the performance characteristics (e.g., switching speed) and size of the transistor are functions of the size.(e.g., width) of the transistor""s gate, and the placement of the source and drain regions. Thus, for example, a narrower gate tends to produce a higher performance transistor (e.g., faster) that is inherently smaller in size (e.g., narrower width).
As is often the case, however, as devices shrink in size from one generation to the next, some of the existing fabrication techniques are not precise enough to be used in fabricating the next generation of integrated circuit devices. For example, spacers are used in conventional semiconductor devices to provide alignment of the source and drain regions to the gates in transistors. Spacers also shadow implants to xe2x80x9cspacexe2x80x9d them away from the transistors.
FIGS. 1-3 illustrate a conventional process for forming spacers on a semiconductor device. In FIG. 1, a cross-section of a portion of a conventional semiconductor device 100 is illustrated. The semiconductor device 100 includes a substrate 110, gate electrodes 120, and gate insulating layers 130. The gate electrodes 120 are formed on the substrate 110 and may include some type of polysilicon, such as an undoped poly, an amorphous poly, a doped poly, a poly with silicide on top, etc. The gate electrodes 120 are typically insulated from the substrate 110 by a thin gate insulating layer 130 made of oxide or oxide-nitride-oxide (ONO).
In FIG. 2, a spacer layer 210 is formed over the substrate 110 and gate electrodes 120 using well known deposition techniques, such as chemical vapor deposition (CVD) or tetraethyl orthosilicate (TEOS) deposition techniques. The spacer layer 210 may include an oxide or nitride insulator, such as silicon oxide, silicon nitride, or silicon-oxynitride.
In FIG. 3, the semiconductor device 100 is subjected to anisotropic etching to etch the spacer layer 210 material to form a spacer 310 along the edges of the gate electrodes 120. The anisotropic etch is typically a plasma reactive-ion etch employing a fluorine-based gas chemistry, such as CF4, CHF3, SF6, C4F8, CH3F, etc., diluted with an inert gas, such as Argon or Helium, or a chlorine or bromine based etch. The conformal nature of the spacer layer 210 deposition produces thicker films at the edges of a gate electrode 120 than on the flat areas. The directional nature of the anisotropic etch removes the same amount of space layer 210 material vertically in all places, leaving a spacer 310 next to the edge of the gate electrode 120.
During the etching process, the silicon 320 between the transistors may be damaged by the plasma etch. It is also possible that the gate insulating layer 130 can be charged when exposed to plasma and, thus, damaged. Such damage may cause current to leak between adjacent transistors on the semiconductor device 100.
There exists a need for a spacer etch process that prevents damage-induced leakage current. This and other needs are met by the present invention, where a two-step etching process is implemented. The two-step etching process includes a combination of anisotropic and isotropic etching to prevent the silicon and gate insulating layer from being damaged by the plasma etching process.
Additional advantages and other features of the invention will be set forth in part in the description that follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of forming spacers on a semiconductor device. The method includes depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a portion of the spacer layer covering the semiconductor device. The semiconductor device is then subjected to an isotropic etching process to form the spacers on the semiconductor device.
In another implementation consistent with the present invention, a method prevents damage-induced leakage current when forming spacers on a semiconductor device multiple gate electrodes. The method includes depositing an insulation layer on the semiconductor device to a first thickness; anisotropically etching the insulation layer to remove a portion of the insulation layer, a remaining portion of the insulation layer being of a second thickness; and isotropically etching the insulation layer of the second thickness to form the spacers adjacent to the gate electrodes on the semiconductor device.
In yet another implementation consistent with the present invention, a spacer etch method includes subjecting a semiconductor device having a spacer layer deposited thereon to an anisotropic etching process to leave approximately 200-400 xc3x85 of the spacer layer covering the semiconductor device; and subjecting the semiconductor device to an isotropic etching process to form one or more spacers on the semiconductor device.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.